Computer Architecture

BSc - Spring Semester
2419, Lectures and exercises, 5.0 ECTS

Lecturer Dr. Markus Anwander
Teaching assistants Sepehr Sameni
Alp Sari
Viktor Shipitsin
Location Hörsaal A006 ExWi Building Sidlerstrasse 5
Time Tuesdays 13:15 - 15:15 (lecture) and 15:15 to 16:00 (tutorials)

Course description

In computer science there are many applications, such as computer simulations, financial transactions and medical telesurgery, where performance is of paramount importance. To write successful programs for such applications, a programmer needs to understand what factors affect performance. This course shows a deep analysis of these factors and how they depend on how both hardware and software are combined in the context of computer organization and design. The course provides a brief introduction to C programming language and then proceeds with the MIPS assembly language, the analysis of computer performance, the description of the computer architecture and advanced technics to gain performance such as pipelining, dealing with hazards, memory architectures, and I/O systems.


1. Students will learn how the major components of a computer including CPU, memory, I/O and storage operate and are interconnected.
2. Students will learn the uses for cache memory.
3. Students will learn a wide variety of memory technologies both internal and external.
4. Students will learn the basic components of the CPU including the ALU and control unit.
5. Students will learn the MIPS assembly programming language.
6. Students will learn the C programming language basics.
7. Students will learn design principles in instruction set design including RISC architectures.
8. Students will learn how GPUs work

Schedule and material

The following table provides an overview of the content of the lectures during the semester. Please check it periodically as it might be updated.

Week Lecture Reading
1 C Introduction ILIAS
3 MIPS Instruction Set Architecture "Patterson&Hennessy", Chapt. 2
4 MIPS Instruction Set Architecture "Patterson&Hennessy", Chapt. 2
5 Performance "Patterson&Hennessy", Chapt. 3,4
6 MIPS Basic Architecture "Patterson&Hennessy", Chapt. 3,4
7 MIPS Basic Architecture "Patterson&Hennessy", Chapt. 3,4
8 Pipeline "Patterson&Hennessy", Chapt. 4
9 Data Hazards "Patterson&Hennessy", Chapt. 4
10 Control Hazards "Patterson&Hennessy", Chapt. 4
11 Multiple Issue Introduction "Patterson&Hennessy", Chapt. 4
12 Memory and Cache Introduction "Patterson&Hennessy", Chapt. 5
13 Cache Performance, IO Systems "Patterson&Hennessy", Chapt. 6
14 Revision ILIAS